The present invention relates generally to analog multiplier circuits, and more particularly to improvements to correct for transistor base current and gain limitations, input offset variations, and limited accuracy and linearity range in conventional analog multipliers.
The prior art includes the article “MOS stacked differential pair multipliers”, J. L. Dawson and A. Hadiashar “A Chopper Stabilized CMOS Analog Multiplier with Ultra Low DC Offsets”, IEEE European Solid State Circuits Conference, in Montreux, Switzerland, pages 364-367, September, 2006. The prior art also includes the assignee's INA210 current shunt monitor circuit, which only measures the voltage across a current shunt and provides a scaled representation of that voltage.
Chopped MOS stacked differential pairs are disclosed in the above mentioned Dawson and Hadiashar article and are used in a 4-quadrant multiplier in which the multiplier inputs and outputs are differential. The chopping scheme illustrated is complex because it chops one set of inputs and “un-chops” the output, and then it chops another set of inputs and again un-chops the output, in a complex 4-quadrant fashion in order to maintain the correct output signal polarity. It is impractical to correct the gain errors of MOS stacked differential pair multipliers because the transconductance of a MOS differential pair drifts with temperature and changes with the differential input voltage. Furthermore, MOS stacked differential pair multipliers as disclosed in the Dawson and Hadiashar article are accurate only for very small voltage magnitude inputs.
The topology of MOS stacked differential pair multipliers, which sometimes have been referred to as Gilbert multipliers, is significantly different from the subsequently described conventional basic translinear Gilbert multiplier invented by Barry Gilbert. The MOS stacked differential pair multipliers use one differential input pair of MOS transistors, controlled by one voltage input, to feed the tail currents of other differential pairs controlled by the second voltage input, in contrast to translinear Gilbert multipliers, which are composed of bipolar transistors and rely on the logarithmic/exponential characteristic of bipolar transistors.
The closest prior art is believed to include a conventional translinear bipolar Gilbert multiplier, which is composed of bipolar transistors rather than MOS transistors and is hereinafter referred to as a “translinear Gilbert multiplier” to clearly distinguish it from MOS multipliers which are sometimes also referred to as Gilbert multipliers.
FIG. 1 shows a conventional translinear Gilbert multiplier 1-1 which includes bipolar NPN transistors Q0 and Q1 each having its emitter connected to conductor 4. An input current IY flows out of conductor 4, and is a single-ended input current of translinear Gilbert multiplier 1-1. The base of transistor Q0 is connected by conductor 2 to the emitter of a diode-connected NPN transistor Q2, the base and collector of which are connected by conductor 7 to VDD. An input current IX+ flows out of conductor 2. The collector of transistor Q0 is connected to an output conductor 5 into which a multiplier output current IMout+ flows. Similarly, the base of transistor Q1 is connected by conductor 3 to the emitter of a diode-connected NPN transistor Q3, the base and collector of which are connected by conductor 7 to VDD. An input current IX− flows out of conductor 3, and the current IX+−IX− constitutes a differential input current of translinear Gilbert multiplier 1-1. The collector of transistor Q1 is connected to an output conductor 6 into which a multiplier output current IMout− flows.
The average of IX+ and IX− is equal to (IX++IX−)/2 and is referred to as the reference current Iref, and the two differential quantities IMOut+−IMOut− and VMOut+−VMOut− are the “multiplier results”.
Chopping is a well known technique for eliminating input offset voltages in operational amplifiers and the like. Chopping continually swaps the two amplifier inputs. Since the inputs of an operational amplifier usually are at essentially the same voltage except for the amplifier input offset voltage which is only a few millivolts, the input node voltages do not change very much as they are swapped during the chopping operation. That means any parasitic capacitance associated with those nodes does not receive and discharge very much charge when going from one chopping state to the other.
However, chopping of relatively high current input signals of an amplifier ordinarily would be avoided because it would result in relatively large signal swings in response to the steep rising and falling edges of the chopping signal. Such large signal swings would be problematic. For example, in a chopped operational amplifier with feedback, the voltage excursions at the feedback input of the operational amplifier are very small, typically only a few millivolts. Since there is a “virtual short circuit” between the input terminals of an operational amplifier with feedback, the chopping or swapping (i.e., the swapping of the two inputs) results in the swapping or interchanging of two conductors of voltages which differ only by a few millivolts of input offset voltage of the operational amplifier. Consequently, the operational amplifier output only needs to move the feedback input of the operational amplifier a few millivolts to maintain the required virtual input short circuit. That results in very fast settling of the output and the feedback input of the operational amplifier. In a conventional operational amplifier, one ordinarily would not chop the operational amplifier inputs if it was necessary for them to change by hundreds of millivolts or more because of the resulting capacitance charging issues and voltage settling issues with the amplifier.
Chopping is impractical in most current mode circuits because it results in large voltage swings, especially at high impedance nodes. The large voltage swings cause various signal settling problems. The operational amplifier has to settle to its final values within the chopping cycle time frame in order to avoid large circuit operating errors. Furthermore, the capacitance associated with the operational amplifier signal terminals may need to be supplied with a significant amount of current in order to charge the terminals to their final voltages.
The gain of the above described translinear Gilbert multiplier cell is much more stable than the gain of the MOS stacked pair multiplier cell. The gain of the translinear Gilbert multiplier cell varies by approximately ±7%, whereas the gain of the MOS stacked pair multiplier cell varies by roughly ±30% or more due to process and temperature variations. However, conventional translinear Gilbert multiplier circuits suffer from various effects that have made them unsuitable for achieving current shunt power measurement accuracies with errors in the ±1% range. Nevertheless, there would be a substantial market for an economical analog multiplier that is capable of achieving accuracy wherein the errors are within the ±1% range or better over widely varying multiplier inputs.
Thus, there is an unmet need for an analog multiplier that is substantially more accurate than the closest prior art MOS stacked differential pair multipliers and translinear Gilbert multipliers.
There also is an unmet need for an analog multiplier which is capable of providing accuracies wherein the errors due to input offset voltage variations and gain variations are within a range of ±1% deviation from ideal.
There also is an unmet need for an analog multiplier which is capable of being used in a current shunt monitor circuit which provides power measurement accuracy wherein the errors are within a range of approximately ±1% deviation from ideal over a wide range of temperature and integrated circuit manufacturing process variations.